| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-02-17 | ARMeilleure: Thumb support (All T16 instructions) (#3105)1.1.36 | merry | 1 | -0/+3 |
| 2022-02-08 | ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)1.1.21 | merry | 1 | -0/+2 |
| 2022-02-06 | ARMeilleure: A32: Implement SHADD8 (#3086)1.1.18 | merry | 1 | -0/+1 |
| 2022-01-19 | Implement FCVTNS (Scalar GP) (#2953) | sharmander | 1 | -0/+1 |
| 2022-01-04 | CPU - Implement FCVTMS (Vector) (#2937) | sharmander | 1 | -0/+1 |
| 2021-12-19 | Implement CSDB instruction (#2927) | gdkchan | 1 | -0/+1 |
| 2021-12-08 | Implement UHADD8 instruction (#2908) | Piyachet Kanda | 1 | -0/+1 |
| 2021-06-23 | Implement VORN (register) Arm32 instruction (#2396) | gdkchan | 1 | -0/+1 |
| 2021-03-25 | Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139) | LDj3SNuD | 1 | -0/+2 |
| 2021-02-22 | Implement VCNT instruction (#1963) | mageven | 1 | -0/+1 |
| 2021-01-26 | Implement PRFM (register variant) as NOP (#1956) | mageven | 1 | -1/+1 |
| 2021-01-20 | CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests... | LDj3SNuD | 1 | -0/+2 |
| 2021-01-04 | CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian... | LDj3SNuD | 1 | -0/+1 |
| 2020-12-16 | CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776) | sharmander | 1 | -0/+1 |
| 2020-12-07 | CPU: Implement VFNMA.F32 | F.64 (#1783) | sharmander | 1 | -0/+1 |
| 2020-12-03 | CPU: Implement VFNMS.F32/64 (#1758) | sharmander | 1 | -0/+1 |
| 2020-10-13 | Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths... | LDj3SNuD | 1 | -0/+7 |
| 2020-08-31 | CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492) | LDj3SNuD | 1 | -0/+2 |
| 2020-08-13 | Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471) | LDj3SNuD | 1 | -0/+2 |
| 2020-07-19 | Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192) | Valentin PONS | 1 | -0/+3 |
| 2020-07-17 | CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390) | LDj3SNuD | 1 | -0/+2 |
| 2020-07-13 | Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335) | LDj3SNuD | 1 | -0/+6 |
| 2020-06-24 | Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303) | riperiperi | 1 | -0/+2 |
| 2020-05-27 | Add FMaxNmV & FMinNmV Inst.s with Test. (#1279) | LDj3SNuD | 1 | -0/+2 |
| 2020-03-24 | Add Fcvtas_S/V & Fcvtau_S/V. (#1018) | LDj3SNuD | 1 | -0/+4 |
| 2020-03-14 | Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982) | riperiperi | 1 | -0/+1 |
| 2020-03-11 | Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other... | gdkchan | 1 | -0/+5 |
| 2020-03-10 | Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960) | gdkchan | 1 | -1/+3 |
| 2020-03-01 | Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954) | gdkchan | 1 | -3/+9 |
| 2020-03-01 | Implement FACGE and FACGT (Scalar and Vector) AArch64 SIMD instructions (#956) | gdkchan | 1 | -0/+4 |
| 2020-02-24 | Add most of the A32 instruction set to ARMeilleure (#897) | riperiperi | 1 | -1/+125 |
| 2019-10-24 | Add Sli_S/V & Sri_S/V inst.s (fast & slow paths), with Tests. (#797) | LDj3SNuD | 1 | -0/+3 |
| 2019-10-04 | Add Tbx Inst. (fast & slow paths), with Tests. (#782) | LDj3SNuD | 1 | -1/+2 |
| 2019-08-08 | Add a new JIT compiler for CPU code (#693) | gdkchan | 1 | -0/+459 |
