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2022-07-06Implement CPU FCVT Half <-> Double conversion variants (#3439)1.1.165gdkchan2-264/+539
2022-05-31Refactor CPU interface to allow the implementation of other CPU emulators (#3...1.1.134gdkchan2-10/+10
2022-03-19InstEmitMemoryEx: Barrier after write on ordered store (#3193)1.1.77merry2-10/+15
2022-03-05A32: Fix ALU immediate instructions (#3179)1.1.60merry1-1/+1
2022-03-04Decoder: Exit on trapping instructions, and resume execution at trapping inst...1.1.58merry2-13/+29
2022-03-04T32: Implement B, B.cond, BL, BLX (#3155)1.1.57merry3-8/+3
2022-02-22T32: Implement ALU (shifted register) instructions (#3135)1.1.53merry2-1/+18
2022-02-22A32: Fix BLX and BXWritePC (#3151)1.1.48merry2-2/+2
2022-02-18Enable CPU JIT cache invalidation (#2965)1.1.44gdkchan2-3/+14
2022-02-18Decoders: Add IOpCode32HasSetFlags (#3136)1.1.39merry1-1/+1
2022-02-17ARMeilleure: Thumb support (All T16 instructions) (#3105)1.1.36merry8-42/+88
2022-02-17Use ReadOnlySpan<byte> compiler optimization for static data (#3130)1.1.34Berkan Diler2-11/+12
2022-02-11InstEmitMemory32: Literal loads always have word-aligned PC (#3104)1.1.26merry2-1/+15
2022-02-08ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)1.1.21merry2-0/+47
2022-02-06ARMeilleure: A32: Implement SHADD8 (#3086)1.1.18merry2-15/+38
2022-01-29Fix small precision error on CPU reciprocal estimate instructions (#3061)1.1.13gdkchan1-1/+1
2022-01-21Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)gdkchan1-3/+1
2022-01-19Implement FCVTNS (Scalar GP) (#2953)sharmander2-0/+13
2022-01-16Fix return type mismatch on 32-bit titles (#3000)gdkchan2-3/+8
2022-01-04CPU - Implement FCVTMS (Vector) (#2937)sharmander2-0/+13
2021-12-19Implement CSDB instruction (#2927)gdkchan3-5/+11
2021-12-08Implement UHADD8 instruction (#2908)Piyachet Kanda2-0/+19
2021-09-29Use normal memory store path for DC ZVA (#2693)riperiperi1-1/+1
2021-09-14Refactor `PtcInfo` (#2625)FICTURE71-1/+1
2021-08-27Implement MSR instruction for A32 (#2585)Mary1-0/+39
2021-08-17Reduce JIT GC allocations (#2515)FICTURE740-98/+105
2021-06-23Implement VORN (register) Arm32 instruction (#2396)gdkchan2-0/+19
2021-05-29Add multi-level function table (#2228)FICTURE73-204/+43
2021-05-24POWER - Performance Optimizations With Extensive Ramifications (#2286)riperiperi1-16/+54
2021-05-24Improve accuracy of reciprocal step instructions (#2305)gdkchan1-26/+95
2021-05-20Use branch instead of tailcall for recursive calls (#2282)FICTURE71-1/+8
2021-05-20Add `BIC/ORR Vd.T, #imm` fast path (#2279)FICTURE72-4/+64
2021-05-13Fold constant offsets and group constant addresses (#2285)gdkchan1-6/+13
2021-04-18Add inlined on translation call counting (#2190)FICTURE72-16/+9
2021-04-02Improve `StoreToContext` emission (#2155)FICTURE71-15/+12
2021-03-25Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)LDj3SNuD3-36/+60
2021-02-22Implement VCNT instruction (#1963)mageven5-9/+42
2021-02-17Fix memory tracking performance regression (#2026)gdkchan1-3/+3
2021-02-16Validate CPU virtual addresses on access (#1987)gdkchan2-114/+41
2021-01-28Lower precision of estimate instruction results to match Arm behavior (#1943)gdkchan1-18/+65
2021-01-26Implement PRFM (register variant) as NOP (#1956)mageven2-2/+2
2021-01-25Add VCLZ.* fast path (#1917)FICTURE72-8/+144
2021-01-20CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests...LDj3SNuD3-14/+89
2021-01-04CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian...LDj3SNuD5-23/+178
2020-12-17Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow...LDj3SNuD4-59/+73
2020-12-17PPTC Follow-up. (#1712)LDj3SNuD1-0/+3
2020-12-16CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)sharmander2-0/+16
2020-12-16Clear JIT cache on exit (#1518)gdkchan4-34/+35
2020-12-15CPU: Implement VFMA (Vector) (#1762)sharmander2-0/+29
2020-12-13Fix register read after write on STREX implementation (#1801)gdkchan1-1/+18
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