| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-08-17 | Reduce JIT GC allocations (#2515) | FICTURE7 | 1 | -2/+3 |
| 2021-02-22 | Implement VCNT instruction (#1963) | mageven | 1 | -0/+28 |
| 2021-01-04 | CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian... | LDj3SNuD | 1 | -23/+13 |
| 2020-12-17 | Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow... | LDj3SNuD | 1 | -53/+49 |
| 2020-12-15 | CPU: Implement VFMA (Vector) (#1762) | sharmander | 1 | -0/+17 |
| 2020-12-07 | CPU: Implement VFNMA.F32 | F.64 (#1783) | sharmander | 1 | -0/+15 |
| 2020-12-03 | CPU: Implement VFNMS.F32/64 (#1758) | sharmander | 1 | -0/+15 |
| 2020-10-13 | Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths... | LDj3SNuD | 1 | -0/+35 |
| 2020-08-13 | Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471) | LDj3SNuD | 1 | -2/+36 |
| 2020-07-17 | CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394) | LDj3SNuD | 1 | -5/+5 |
| 2020-07-17 | CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390) | LDj3SNuD | 1 | -0/+14 |
| 2020-07-13 | Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335) | LDj3SNuD | 1 | -2/+2 |
| 2020-06-24 | Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303) | riperiperi | 1 | -1/+61 |
| 2020-06-16 | Add Profiled Persistent Translation Cache. (#769) | LDj3SNuD | 1 | -27/+27 |
| 2020-03-11 | Implement VMULL, VMLSL, VRSHR, VQRSHRN, VQRSHRUN AArch32 instructions + other... | gdkchan | 1 | -79/+124 |
| 2020-03-05 | Implement Fast Paths for most A32 SIMD instructions (#952) | jduncanator | 1 | -115/+642 |
| 2020-02-24 | Add most of the A32 instruction set to ARMeilleure (#897) | riperiperi | 1 | -0/+634 |
